In a typical computer system, a central processing unit (CPU) of the system supports various power states to allow robust power management in the system. For example, a CPU may support five power states, such as the C0, C1, C2, C3, and C4 states. In one system, the C0 state is an active power state, in which the CPU executes instructions, while the remaining states, i.e., the C1, C2, C3, and C4 states, are sleeping states. In the sleeping states, the CPU consumes less power and dissipates less heat than in the C0 state because the CPU does not execute any instruction while in the sleeping states. Furthermore, the power consumption in the C4 state is generally less than the power consumption in the C3 state because the CPU supply voltage is lowered when the CPU enters into the C4 state.
Each sleeping state has a latency associated with entering and exiting and is related to the power saving in each state. In general, the more circuitry or logic being shutdown to save more power, the more effort and longer exit latency are consumed to re-energize the circuitry and/or logic shutdown. For example, the phase lock loop (PLL) and input/output (IO) of a CPU can be shut down to save more power when the CPU is in the C3 or C4 state because the CPU does not snoop while in the C3 or C4 state. However, it typically takes longer to re-energize the PLL and IO after the CPU exits from the C3 or C4 state.
In an exemplary system, the CPU can access the memory during the C0 state or snoop bus-master initiated memory traffic while in the C1 or C2 state. The bus master is a peripheral device having control of the bus at a given time, such as, for example, an external graphic core. The data movement from one device to another over a bus is, therefore, referred to as a bus mastering event. In contrast, in the C3 or C4 state, the CPU suspends snooping or memory access as part of the deeper sleep states. In order to snoop the bus-master initiated memory traffic, a CPU in either the C3 or C4 state has to exit the C3 or C4 state. Because of the higher exit latency of the C3 and C4 states, the system has to verify whether there is an on-going bus mastering event from any peripheral device in the system that may require the CPU to snoop before entering either the C3 or C4 state. If there is an on-going bus mastering event, the CPU has to settle for a power state (e.g., C1 or C2) with higher power consumption but lower exit latency than the C3 or C4 state.
As to the peripheral device, it may be coupled to the CPU through a root complex device via a serial interconnect, such as a PCI EXPRESS interconnect. A root complex device includes a host bridge and one or more root ports. Examples of a root complex device include a memory controller or IO controller functional device. An interconnect is an infrastructure that couples one device to another. PCI EXPRESS is a high speed, point-to-point serial interconnect standard. For example, the first generation of PCI EXPRESS interconnect supports 2.5 Gb/sec per lane data transmission. In one exemplary system, a graphic device is coupled to a chipset of the system (e.g., a memory controller hub) through a 16-lane PCI Express interconnect.
Furthermore, PCI EXPRESS allows flow control by supporting an accounting scheme with credits to keep track of the traffic over a PCI EXPRESS interconnect. The credits indicate the available buffering in a device for various types of transactions over an interconnect. For example, a memory controller can report to the software of the capability of a root complex device to transmit data by writing the information in a number of registers. According to PCI EXPRESS protocol, there are a number of prescribed credits for various transactions, such as, read request, write request, completion, etc. For example, when a graphic device issues transactions (e.g., read requests) towards the root complex device and these transactions are pending, a credit is consumed to reflect the amount of buffering taken up in the memory controller by the pending transactions. When these transactions are handled or retired by the memory controller, the credit is released or freed up. The number of pending transactions, as reflected by the credits consumed, indicates the likelihood of a bus mastering event that may prohibit entry into the C3 or C4 state.
A prior art technique to indicate on-going bus mastering traffic uses a sideband signal. For example, a graphic device sends a signal AGP_BUSY to the root complex device of the computer system to indicate on-going bus mastering traffic for the system that attaches the graphic device using Accelerated Graphics Port (AGP). However, the sideband signals are costly because they require one additional pin per sideband signal on each device. Furthermore, permanent connector infrastructure has to be provided for the sideband signals in the system even though future technological innovation may not use such sideband signals at all.